2025-05-28 14:41:02 -05:00
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#ifndef _PCI_H
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#define _PCI_H
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2025-07-01 20:39:38 -05:00
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#include <types.h>
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struct pci_header {
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command;
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uint16_t status;
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uint8_t revision_id;
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uint8_t prog_if;
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uint8_t subclass;
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uint8_t class_code;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist;
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} __attribute__((packed));
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struct pci_header_type_0 {
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command;
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uint16_t status;
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uint8_t revision_id;
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uint8_t prog_if;
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uint8_t subclass;
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uint8_t class_code;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist;
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uint32_t bar0;
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uint32_t bar1;
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uint32_t bar2;
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uint32_t bar3;
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uint32_t bar4;
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uint32_t bar5;
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uint32_t cardbus_cis_ptr;
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uint16_t subsystem_vendor_id;
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uint16_t subsystem_id;
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uint32_t expansion_rom_base;
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uint8_t capabilities_ptr;
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uint8_t reserved1[3];
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uint32_t reserved2;
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint8_t min_grant;
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uint8_t max_latency;
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} __attribute__((packed));
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2025-05-28 14:41:02 -05:00
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uint32_t pci_config_read(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset);
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void pci_config_write(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset, uint32_t value);
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void pci_enumerate(void);
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#endif
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