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0.0.2d: Added BGA support, graphics!

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This commit is contained in:
David Goeke
2026-06-05 16:14:14 -05:00
parent 5971218b56
commit f3b2f95af5
40 changed files with 1007 additions and 1197 deletions
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132
drivers/pci.c
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@ -17,96 +17,104 @@
uint32_t pci_config_read(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset)
{
uint32_t address = 0;
address |= (bus << 16); /* Bus number (bits 23-16) */
address |= (device << 11); /* Device number (bits 15-11) */
address |= (function << 8); /* Function number (bits 10-8) */
address |= (offset & 0xFC); /* Register offset (bits 7-0) */
address |= (1 << 31); /* Enable configuration access */
uint32_t address = 0;
address |= (bus << 16); /* Bus number (bits 23-16) */
address |= (device << 11); /* Device number (bits 15-11) */
address |= (function << 8); /* Function number (bits 10-8) */
address |= (offset & 0xFC); /* Register offset (bits 7-0) */
address |= (1 << 31); /* Enable configuration access */
outl(PCI_CONFIG_ADDRESS, address); /* Write address to PCI config space */
return inl(PCI_CONFIG_DATA); /* Read data from PCI config space */
outl(PCI_CONFIG_ADDRESS, address); /* Write address to PCI config space */
return inl(PCI_CONFIG_DATA); /* Read data from PCI config space */
}
void pci_config_write(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset, uint32_t value)
{
uint32_t address = 0x80000000 | (bus << 16) | (device << 11) | (function << 8) | (offset & 0xFC);
outl(PCI_CONFIG_ADDRESS, address); /* Send the address to PCI config space */
outl(PCI_CONFIG_DATA, value); /* Write data to PCI config space */
uint32_t address = 0x80000000 | (bus << 16) | (device << 11) | (function << 8) | (offset & 0xFC);
outl(PCI_CONFIG_ADDRESS, address); /* Send the address to PCI config space */
outl(PCI_CONFIG_DATA, value); /* Write data to PCI config space */
}
void pci_config_read_block(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset, void* buffer, size_t size)
{
uint8_t* buf = (uint8_t*)buffer;
uint8_t* buf = (uint8_t*)buffer;
for (size_t i = 0; i < size; i += 4)
{
uint32_t value = pci_config_read(bus, device, function, offset + i);
for (size_t i = 0; i < size; i += 4)
{
uint32_t value = pci_config_read(bus, device, function, offset + i);
size_t remaining = size - i;
if (remaining >= 4)
{
*(uint32_t*)(buf + i) = value;
size_t remaining = size - i;
if (remaining >= 4)
{
*(uint32_t*)(buf + i) = value;
}
else
{
for (size_t j = 0; j < remaining; ++j)
{
buf[i + j] = (value >> (8 * j)) & 0xFF;
}
}
}
else
{
for (size_t j = 0; j < remaining; ++j)
{
buf[i + j] = (value >> (8 * j)) & 0xFF;
}
}
}
}
void pci_init(void)
{
#ifdef _DEBUG
printf("[ PCI ] Initializing PCI...\n");
printf("[ PCI ] Initializing PCI...\n");
#endif
pci_enumerate();
pci_enumerate();
#ifdef _DEBUG
printf("[ PCI ] PCI initialized\n");
printf("[ PCI ] PCI initialized\n");
#endif
}
void pci_enumerate(void)
{
for (uint16_t bus = 0; bus < 256; bus++) /* Maximum 256 buses */
{
for (uint8_t device = 0; device < 32; device++) /* Maximum 32 devices per bus */
for (uint16_t bus = 0; bus < 256; bus++) /* Maximum 256 buses */
{
for (uint8_t function = 0; function < 8; function++) /* Maximum 8 functions per device */
{
struct pci_header pre_header;
pci_config_read_block(bus, device, function, 0x00, &pre_header, sizeof(pre_header));
for (uint8_t device = 0; device < 32; device++) /* Maximum 32 devices per bus */
{
for (uint8_t function = 0; function < 8; function++) /* Maximum 8 functions per device */
{
struct pci_header pre_header;
pci_config_read_block(bus, device, function, 0x00, &pre_header, sizeof(pre_header));
if (pre_header.vendor_id == 0xFFFF)
{
continue; /* No device present */
}
if (pre_header.class_code == 0xB)
{
printf("Processor found on PCI bus, what?!?!\n"); /* For some stupid reason, processors can be on the PCI bus? */
continue;
}
if (pre_header.header_type == 0x00)
{
struct pci_header_type_0 hdr;
pci_config_read_block(bus, device, function, 0x00, &hdr, sizeof(hdr));
if (pre_header.vendor_id == 0xFFFF)
{
continue; /* No device present */
}
if (hdr.class_code == 0x1 && hdr.subclass == 0x6 && hdr.prog_if == 0x1)
{
/*configure_ahci_controller(hdr);*/
}
/*printf("PCI device: cc: %x sc: %x pi: %x b: %x d: %x f: %x int: %x\n", hdr.class_code, hdr.subclass, hdr.prog_if, bus, device, function, (uint32_t) hdr.interrupt_line);*/
if (pre_header.class_code == 0xB)
{
printf("Processor found on PCI bus, what?!?!\n"); /* For some stupid reason, processors can be on the PCI bus? */
continue;
}
if (pre_header.header_type == 0x00)
{
struct pci_header_type_0 hdr;
pci_config_read_block(bus, device, function, 0x00, &hdr, sizeof(hdr));
if (hdr.class_code == 0x1 && hdr.subclass == 0x6 && hdr.prog_if == 0x1)
{
/*configure_ahci_controller(hdr);*/
}
if (hdr.class_code == 0x03)
{
uint32_t bar0 = hdr.bar0;
extern void init_bga_framebuffer(uint32_t* _p);
init_bga_framebuffer((uint32_t*) bar0);
printf("Found framebffer addr 0x%x on device %x \n", bar0, hdr.device_id);
}
/*printf("PCI device: cc: %x sc: %x pi: %x b: %x d: %x f: %x int: %x\n", hdr.class_code, hdr.subclass, hdr.prog_if, bus, device, function, (uint32_t) hdr.interrupt_line);*/
}
}
}
}
}
}
}